1. Field of the Invention
The present invention relates to a regulator circuit used in a power conversion device such as an internal combustion engine ignition device, and to a semiconductor integrated circuit device forming the regulator circuit. More particularly, the invention relates to a regulator circuit wherein it is possible to output a voltage which enables a load circuit (one or more circuits serving as a load of the regulator circuit) to operate normally despite a momentary interruption or momentary drop of an external power supply voltage, and to a semiconductor integrated circuit device forming the regulator circuit.
2. Description of the Prior Art
FIG. 8 is a main portion circuit diagram of a commonly used regulator circuit 500 which lowers an external power supply voltage VB. With, for example, a band gap reference circuit used as a reference voltage circuit 55, it is possible to make an output voltage VREG of the regulator circuit 500 a stable voltage to which is added a reference voltage VREF division ratio of resistors (a first resistor 65 and second resistor 66) by using a reference voltage, having no temperature dependence (the reference voltage actually has some temperature dependence, but it is taken here that it has no temperature dependence), which is generated from the reference voltage circuit 55. By setting a current flowing through an MOSFET 56 (an enhancement type n-channel type MOSFET) connected to an external power supply voltage terminal VB into which an external power supply voltage is input (a terminal into which is input an external power supply voltage such as a battery voltage) to be equal to or higher than a current flowing through a load circuit 70, it is possible to make the output voltage VREG of the regulator circuit 500 a set voltage VREG0 which is a constant voltage. It is possible to raise the VREG from the low external power supply voltage VB by using a depression type MOSFET as the MOSFET 56.
Of the reference signs in FIG. 8, 52 is a positive terminal of an operational amplifier 51, 53 is a negative terminal of the operational amplifier 51, 54 is an output terminal of the operational amplifier 51, 57 is a drain of the MOSFET 56, 58 is a source of the MOSFET 56, 59 is a gate of the MOSEFT 56, 65 is the first resistor, 66 is the second resistor, 67 is a first connection point, 68 is a second connection point, 69 is an output terminal of the regulator circuit 500, VB is the external power supply voltage, and VDD is a power supply which drives the operational amplifier 51.
FIGS. 9A and 9B are diagrams showing a behavior of the VB when momentarily interrupted in the regulator circuit 500 of FIG. 8, wherein FIG. 9A is a waveform diagram of the VB, while FIG. 9B is a waveform diagram of the VREG. Herein, the VB is substantially equal to the VREG in a range from VB=0V until the VB rises, but when an enhancement type MOSFET is used, there is originally a region in which the VB drops by the amount of the threshold voltage of the enhancement type MOSFET. An operation of a depression type MOSFET is shown for the sake of simplification. When the VB falls below the VREG and drops to, for example, 0V, the VREG also drops to 0V following the VB. In normal operation, an unshown capacitor (which is small in capacitance particularly when the load circuit is configured of a semiconductor integrated circuit) configuring each of the load circuit 70 is in a condition in which it is charged with the VREG. When a momentary interruption occurs in the VREG, electric charge with which the capacitor is charged is discharged via the external power supply voltage terminal (VB terminal) to an external power supply (battery) side, thus reverse charging the unshown external power supply.
When the capacitor is low in capacitance, the discharge is carried out so that the VREG follows the drop of the VB. When the VB drops drastically, the VREG also drops drastically, and a minimum voltage VREG2 of the VREG reaches 0V. When a VREG1 shown by the broken line is set to be a voltage which enables the load circuit 70 to operate normally, it is difficult for the load circuit 70 to operate normally at a point at which VREG2<VREG1. The load circuit 70 has a logic circuit incorporated therein and, for example, a latch circuit configured of the logic circuit cannot maintain a normal state, thus causing malfunction such as latch release.
FIG. 10 is a diagram showing VB dependence of the VREG. This shows VB dependence when the regulator circuit 500 starts operating and stops operating.
The regulator circuit 500 starts operating, and when the VB rises gradually from 0V, the VREG rises following the VB. Because of this, the VB and VREG rise in a relationship of VREG=VB. VREG=VREG0 at a point at which the VB reaches the VREG0, and the VREG is the VREG0 and a constant voltage in a condition in which VB>VREG0. Normally, the regulator circuit 500 operates at the VREG0. Herein, for example, the circle indicates an operating point.
Meanwhile, when the VB drops to 0V from a voltage higher than the VREG0 in a stop and transitional state of the regulator circuit 500, VREG=VREG0 when VB≧VREG0, while VREG=VB in the range of VREG0>VB=0V, and the VREG drops to 0V following the VB.
FIG. 11 is a diagram showing temperature dependence of the VREG. The temperature dependence of the VREG is such that the VREG has no temperature dependence and is flat when using a reference voltage with no temperature dependence, such as of a band gap reference circuit, as previously described. Because of this, the VREG at the operating point coincides with the VREG0, and the VREG is of a constant value without changing with a rise and drop in temperature.
Also, it is disclosed in JP-A-59-96828 (FIG. 2) that, in a parallel redundant system direct current power supply device including a backflow prevention diode on the output side, by adopting a configuration wherein a dummy resistor is used only when necessary, it is possible to reliably carry out the selection of a defective device, and thus possible to contribute to a loss reduction.
Also, the following is disclosed in JP-A-2004-129413 (FIG. 1). A charge pump circuit includes a voltage source, a boosting capacitor, a holding capacitor, and a diode provided so as to prevent a backflow of a discharge current of a capacitor charged by the voltage source, and reduce the output voltage of the charge pump circuit by the amount of forward voltage. The circuit outputs a voltage value greater than that of the output voltage of the voltage source by utilizing the action of charging the capacitors. The circuit also includes a correcting diode provided so as to increase the output voltage of the voltage source by the amount of forward voltage. This configuration prevents the output voltage of the charge pump circuit from being affected by the forward voltage of the diode.
It is disclosed in JP-A-2010-288444 (FIG. 1) to provide a gate drive device, which drives the gate of an active element with high input capacitance, such as an IGBT or MOSFET, including a semiconductor integrated circuit 4 having an internal power supply circuit which forms an internal power source based on an external power source supplied from an external power supply such as a battery. The semiconductor integrated circuit incorporates a voltage drop suppression circuit, and a drop of the internal power supply voltage of the internal power supply circuit to lower than a minimum operating voltage, and a sharp drop of voltage output to the gate, are suppressed by the voltage drop suppression circuit when an input external power supply voltage drops momentarily to lower than a minimum operating voltage. It is disclosed a gate drive device which can thereby suppress a fluctuation in the internal power supply voltage and output voltage while reducing the number of parts by omitting a bypass capacitor connected in parallel to the semiconductor integrated circuit. It is described that a ZD/R parallel circuit wherein a zener diode ZD and resistor R are connected in parallel to the internal power supply circuit is provided in the gate drive circuit. A description is given, in FIGS. 12 to 15, of a case in which the ZD/R parallel circuit is provided in a regulator circuit which lowers the external power supply voltage.
However, with the regulator circuit 500 of FIG. 8, when there is a momentary voltage interruption or momentary voltage drop, the VREG drops to 0V or drops drastically, as shown in FIGS. 9A and 9B. When the VREG drops drastically, the power supply voltage supplied to the load circuit 70 drops drastically, and the minimum value VREG2 of the VREG falls below the minimum voltage (=VREG1) which enables the load circuit 70 to operate normally, thus preventing the load circuit 70 from maintaining the normal operation. For example, the latch circuit malfunctions such as by the latch being released, as previously described. A description will be given of a heretofore known regulator circuit 600 which, in order to prevent this problem, adopts measures to be able to supply a voltage which enables the load circuit 70 to operate normally even when there is a momentary voltage interruption or momentary voltage drop.
FIG. 12 is a main portion circuit diagram of the heretofore known regulator circuit 600 adopting the measures. A ZD/R parallel circuit 60 which is a reverse current limiter circuit wherein a zener diode 61 and resistor 64 are connected in parallel is connected on the output terminal 69 side (downstream side) of the regulator circuit 500 of FIG. 8. The ZD/R parallel circuit 60 is a circuit which, when VB<VREG0, blocks a current Ib flowing from unshown capacitors of the load circuit 70 to the VB terminal via an unshown body diode (parasitic diode) of the MOSFET 56. The zener diode 61 prevents a backflow, but as the resistor 64 causes a reverse current to flow while suppressing it, it is not possible to completely interrupt the reverse current (current Ib).
Also, the resistor 64 is necessary for supplying voltage to the load circuit 70 until a threshold voltage (of on the order of 0.6V) of the zener diode 61 is reached when the VB rises from 0V, as will be described hereafter. Next, a description will be given of an advantageous effect obtained by providing the ZD/R parallel circuit 60. The threshold voltage (=0.6V) of the zener diode 61 is a voltage when a forward voltage rises and a voltage affected by the diffusion potential of a pn junction.
FIGS. 13A and 13B are diagrams of a behavior of the VB when momentarily interrupted in the regulator circuit 600 of FIG. 12, wherein FIG. 13A is a waveform diagram of the VB, while FIG. 13B is a waveform diagram of the VREG. When the external power supply voltage VB is applied to the external power supply voltage terminal (VB terminal), the operational amplifier 51 operates, thereby resulting in that the potential of the negative terminal 53 of the operational amplifier 51, reflecting the voltage of the positive terminal 52, becomes equal to the voltage (VERF) of the positive terminal 52, and the voltage of the second connection point 68 reaches the reference voltage VREF of the operational amplifier 51. By regulating the gate voltage of the MOSFET 56 into which is input an output voltage output from the output terminal 54 of the operational amplifier 51, a current I0 flowing through the second resistor 66 is regulated so that the reference voltage VREF is generated in the second resistor 66. The voltage of the first connection point 67, being ((the resistance value of the first resistor 65+the resistance value of the second resistor 66)/the resistance value of the second resistor 66)×VREF, reaches a set voltage VREG0. Then, VREG=VREG0−Vp, and the VREG is a constant voltage (VREG0−Vp) in the region of VB≧VREG0. The Vp is a voltage drop Vp occurring in the ZD/R parallel circuit 60.
Meanwhile, when the VB is momentarily interrupted, VB<VREG0, and VB=0V in an extreme case. At this time, electric charge within the load circuit 70 is discharged, and a reverse current tends to flow toward the VB terminal via the ZD/R parallel circuit 60 which is a backflow limiter circuit, but is blocked by the zener diode 61, meaning that the reverse current flows via the resistor 64. When the VB voltage<0, the reverse current flows from the GND into the resistor 64 via the body diodes of the series of currents. Consequently, when VB=0V, VREG=VREG2 rather than VREG=0. The VREG2 depends on the current flowing through the resistor 64.
By setting the VREG2 to be equal to or higher than a voltage VREG1) at which the resistor 64 is optimized to enable the load circuit 70 to operate normally, the load circuit 70 can maintain the operation normally even when there is a momentary voltage interruption or momentary voltage drop.
FIG. 14 is a diagram showing VB dependence of the VREG. This shows VB dependence when the regulator circuit 600 starts operating and stops operating.
VREG=VREG0−Vp when VB≧VREG0. Also, VREG=VB−Vp when VB<VREG0. The drop rate of the VREG decreases when the VB is between the threshold voltage (0.6V) of the zener diode 61 and 0V. This is because a voltage (R×Ir1) generated in the resistor 64 is dominant when the Vp is between these voltages. The VREG is supplied to the load circuit 70. The circle in FIG. 14 is an operating point.
FIG. 15 shows temperature dependence of the VREG. Even when the reference voltage VREF has no temperature dependence, the temperature dependence of the voltage drop Vp generated in the ZD/R parallel circuit 60 is reflected in the temperature dependence of the VREG. The temperature dependence of the VREG becomes positive, and the Vp decreases when the temperature rises, while the Vp increases when the temperature drops.
That is, in the regulator circuit 600 shown in FIG. 12, the VREG is a voltage always lower than the VREG0 by the amount of the Vp in the region of VB≧VREG0. Furthermore, as the VREG, reflecting the temperature dependence of the Vp, has the positive temperature dependence, there is a problem that the VREG is not suitable to be used as a power source when it is desired to eliminate temperature dependence in the output characteristics of the load circuit.
Also, in JP-A-59-96828 (FIG. 2) and JP-A-2004-129413 (FIG. 1), a regulator output is stabilized toward a drop in the external power supply voltage to prevent malfunction of the load circuit, thus enabling a circuit operation even at the low external power supply voltage. Furthermore, no description is given of a regulator circuit wherein the VREG has no temperature dependence so that it is possible to supply a voltage which enables the load circuit to operate normally.